Английская Википедия:ARM Cortex-A720
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The ARM Cortex-A720 is a CPU core model from Arm unveiled in TCS23, it serves as a successor of the CPU core ARM Cortex-A715, Cortex-A700 CPU cores series generally focus on high performance and efficiency, the CPU core can be paired with other cores in its family like ARM Cortex-X4 or/and ARM Cortex-A520 in a CPU cluster. It can be used as either "big" or "LITTLE".[1][2][3][4][5][6]
Architecture changes in comparison with ARM Cortex-A715
- 15% peak performance improvement over the Cortex-A715
- Can down to same size as Cortex-A78 with 10% performance improvement
- Down L2 cache hit latency to 9 cycles (from 10 cycles)
- Down mispredict latency to 11 cycles (from 12 cycles)[3]
- x2 L2 bandwidth
- Area optimize configuration for no area cost vs A78
- DSU-120
- Up to 14 cores (up from 12 cores)
- Up to 32 MiB of shared L3 cache (increased from 16 MiB)
- Update to ARMv9.2
Architecture comparison
| uArch | Cortex-A78 | Cortex-A710 | Cortex-A715 | Cortex-A720 |
|---|---|---|---|---|
| Peak clock speed | ~3.0 GHz | |||
| Decode width | 4 | 5 | ||
| Dispatch | 6/cycle | 5/cycle[7] | ? | |
| Max In-flight | 160 | ? | 192+[8] | ? |
| L0 (Mops entries) | 1536[9][10][11] | 0 | ||
| L1-I + L1-D | 32/64+32/64 KiB | |||
| L2 | 128–512 KiB | |||
| L3 | 0–8 MiB | 0–16 MiB | 0-32 MiB | |
| AArch | 32-bit and 64-bit | 64-bit | ||
| Architecture | ARMv8.2-A | ARMv9.0-A | ARMv9.2-A | |
See also
- ARM Cortex-X4, related high performance microarchitecture
- ARM Cortex-A520, related high efficient microarchitecture
- Comparison of ARMv8-A cores
References
Шаблон:Application ARM-based chips
