Английская Википедия:ARM Cortex-X2
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Шаблон:Short description Шаблон:Infobox CPU
The ARM Cortex-X2 is a central processing unit implementing the ARMv9-A 64-bit instruction set designed by ARM Holdings' Austin design centre as part of ARM's Cortex-X Custom (CXC) program.[1]It forms part of Arm's Total Compute Solutions 2021 (TCS21) along with Arm's Cortex-A710, Cortex-A510, Mali-G710 and CoreLink CI-700/NI-700.[2]
Architecture changes in comparison with ARM Cortex-X1
The processor implements the following changes:[3][4][5]
- 10 cycle pipeline down from 11, created by reducing the dispatch stage from 2 cycles to 1
- Reorder buffer (ROB) increased by 30% from 224 entries to 288
- dTLB increased by 20% from 40 entries to 48
- SVE2 SIMD support
- Bfloat16 data type support
- Support for Aarch32 removed
- DSU-110
- Up to 12 cores (up from 8 cores)
- Up to 16M L3 cache (up from 8 MB)
- CoreLink CI-700/NI-700
- Up to 32MB SLC
- ARMv9.0
Performance claims:
- Comparing the Cortex-X2 to the Cortex-X1 with the same process, clock speed, and 4MB of L3 cache (also known as ISO-process):
- 16% greater integer performance / IPC
- 100% greater ML performance
- 30% peak performance improvement over the Cortex-X1 in smartphones (3.3GHz, 1MB L2, 8MB L3)
- 40% faster than an Intel Core i5-1135G7 at 15W (3.5GHz, 1MB L2, 16MB L3)
Usage
- MediaTek Dimensity 9000/9000+[6]
- Qualcomm Snapdragon 7+ Gen 2[7]
- Qualcomm Snapdragon 8/8+ Gen 1[8]
- Samsung Exynos 2200[9]
See also
- ARM Cortex-A710, related high performance microarchitecture
- Comparison of ARMv8-A cores, ARMv8 family
References
Шаблон:Application ARM-based chips