Английская Википедия:ARM Cortex-X4
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The ARM Cortex-X4 is a CPU core model from Arm. unveiled in TCS23, it serves as the successor of The ARM Cortex-X3, X-series CPU cores generally focus on high performance, and can be paired with other cores in its family like ARM Cortex-A720 or/and ARM Cortex-A520 in a CPU cluster.[1][2][3][4]
Architecture changes in comparison with ARM Cortex-X3
The processor implements the following changes:[1][2][3]
- micro-op (MOP) cache: removed (previously 1.5k entries)
- Decode width: 10
- Rename / Dispatch width: 10 (increased from 8)
- Reorder buffer (ROB): 384 entries (increased from 320)
- Execution ports: 21 (increased from 15)
- Pipeline length: 10 (increased from 9)
- Up to 2 MiB of private L2 cache (increased from 1 MiB)
- DSU-120
- Up to 14 cores (up from 12 cores)
- Up to 32 MiB of shared L3 cache (increased from 16 MiB)
- ARMv9.2
Performance claims:
- 15% peak performance improvement over the Cortex-X3 in smartphones (3.4GHz, 2MB L2, 8MB L3).[3]
- 13% IPC uplift over the Cortex-X3, when based on the same process, clock speed, and L3 cache (but 2 MiB L2 vs 1 MiB L2) setup (also known as ISO-process).[3]
Architecture comparison
uArch | Cortex-A78 | Cortex-X1 | Cortex-X2 | Cortex-X3 | Cortex-X4 |
---|---|---|---|---|---|
Peak clock speed | ~3.0 GHz | ~3.25 GHz | ~3.4 GHz | ||
Decode Width | 4 | 5 | 6 | 10[5] | |
Dispatch | 6/cycle | 8/cycle | 10/cycle | ||
Max In-flight | 2x160 | 2x224 | 2x288 | 2x320 | 2x384 |
L0 (Mops entries) | 1536[6] | 3,072[6] | 1536 | None[5] | |
L1-I + L1-D | 32+32 KiB[7] | 64+64 KiB | |||
L2 | 128–512 KiB | 0.256 – 1 MiB | 0.5 – 2 MiB | ||
L3 | 0–8 MiB | 0–16 MiB | 0–32 MiB | ||
Architecture | ARMv8.2 | ARMv9 | ARMv9.2 |
Usage
- MediaTek Dimensity 9300[8]
- Qualcomm Snapdragon 8 Gen 3 (2023)[9]
See also
- ARM Cortex-A720, related efficient sustained performance microarchitecture
- ARM Cortex-A520, related high efficient microarchitecture
- Comparison of ARMv8-A cores
References
Шаблон:Application ARM-based chips