Английская Википедия:10 nm process

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Шаблон:For Шаблон:Use dmy dates Шаблон:Short description Шаблон:Semiconductor manufacturing processes In semiconductor fabrication, the International Technology Roadmap for Semiconductors (ITRS) defines the 10 nm process as the MOSFET technology node following the 14 nm node. 10 nm class denotes chips made using process technologies between 10 and 20 nm.

All production 10 nm processes are based on FinFET (fin field-effect transistor) technology, a type of multi-gate MOSFET technology that is a non-planar evolution of planar silicon CMOS technology. Samsung first started their production of 10 nm-class chips in 2013 for their multi-level cell (MLC) flash memory chips, followed by their SoCs using their 10 nm process in 2016. TSMC began commercial production of 10 nm chips in 2016, and Intel later began production of 10Шаблон:Nbspnm chips in 2018.

Since 1997, however, "node" has become a commercial name for marketing purposes that indicates new generations of process technologies, without any relation to gate length, metal pitch or gate pitch. For example, GlobalFoundries' 7 nm processes are similar to Intel's 10 nm process, thus the conventional notion of a process node has become blurred. TSMC and Samsung's 10 nm processes are somewhere between Intel's 14 nm and 10 nm processes in transistor density. The transistor density (number of transistors per square millimetre) is more important than transistor size, since smaller transistors no longer necessarily mean improved performance, or an increase in the number of transistors.

Background

The ITRS's original naming of this technology node was "11 nm". According to the 2007 edition of the roadmap, by the year 2022, the half-pitch (i.e., half the distance between identical features in an array) for a DRAM should be 11 nm.

In 2008, Pat Gelsinger, at the time serving as Intel's Chief Technology Officer, said that Intel saw a 'clear way' towards the 10 nm node.

In 2011, Samsung announced plans to introduce the 10Шаблон:Nbspnm process the following year. In 2012, Samsung announced eMMC flash memory chips that are produced using the 10Шаблон:Nbspnm process.

In actuality, "10 nm" as it is generally understood in 2018 is only in high-volume production at Samsung. GlobalFoundries has skipped 10 nm, Intel has not yet started high-volume 10 nm production, due to yield issues, and TSMC has considered 10 nm to be a short-lived node, mainly dedicated to processors for Apple during 2017–2018, moving on to 7 nm in 2018.

There is also a distinction to be made between 10 nm as marketed by foundries and 10 nm as marketed by DRAM companies.

Technology production history

In April 2013, Samsung announced that it had begun mass production of multi-level cell (MLC) flash memory chips using a 10Шаблон:Nbspnm-class process, which, according to Tom's Hardware, Samsung defined as "a process technology node somewhere between 10-nm and 20-nm". On 17 October 2016, Samsung Electronics announced mass production of SoC chips at 10 nm. The technology's main announced challenge has been triple patterning for its metal layer.

TSMC began commercial production of 10 nm chips in early 2016, before moving onto mass production in early 2017.

On 21 April 2017, Samsung started shipping their Galaxy S8 smartphone which uses the company's version of the 10 nm processor. On 12 June 2017, Apple delivered second-generation iPad Pro tablets powered with TSMC-produced Apple A10X chips using the 10 nm FinFET process.

On 12 September 2017, Apple announced the Apple A11, a 64-bit ARM-based system on a chip, manufactured by TSMC using a 10 nm FinFET process and containing 4.3 billion transistors on a die of 87.66 mm².

In April 2018, Intel announced a delay in volume production of 10 nm mainstream CPUs until sometime in 2019. In July the exact time was further pinned down to the holiday season. In the meantime, however, they did release a low-power 10 nm mobile chip, albeit exclusive to Chinese markets and with much of the chip disabled.

In June 2018 at VLSI 2018, Samsung announced their 11LPP and 8LPP processes. 11LPP is a hybrid based on Samsung 14 nm and 10 nm technology. 11LPP is based on their 10 nm BEOL, not their 20 nm BEOL like their 14LPP. 8LPP is based on their 10LPP process.

Nvidia released their GeForce 30 series GPUs in September 2020. They are made on a custom version of Samsung's 8 nm process, called Samsung 8N, with a transistor density of 44.56 million transistors per mm².

10 nm process nodes

Foundry

	ITRS Logic Device Ground Rules (2015)		Samsung					TSMC	Intel
Process name	16/14 nm	11/10 nm	10LPE (10 nm)	10LPP (10 nm)	8LPP (8 nm)	8LPU (8 nm)	8LPA (8 nm)	10FF (10 nm)	10nm	10nm SF (10 nm)Шаблон:Efn
Transistor density (MTr / mm2)	Шаблон:Unknown	Шаблон:Unknown	51.82		61.18		?	52.51	100.76Шаблон:Efn
Transistor gate pitch (nm)	70	48	68		64		?	66	54
Interconnect pitch (nm)	56	36	51		?		?	44	36
Transistor fin pitch (nm)	42	36	42		42		?	36	34
Transistor fin height (nm)	42	42	49		?		?	42	53
Production year	2015	2017	Шаблон:Yes	Шаблон:Yes	Шаблон:Yes	Шаблон:Yes	Шаблон:Yes	Шаблон:Yes 2017 production	Шаблон:Yes (Cannon Lake)	Шаблон:Yes (Tiger Lake)

Шаблон:Notelist Transistor gate pitch is also referred to as CPP (contacted poly pitch) and interconnect pitch is also referred to as MMP (minimum metal pitch). Samsung reported their 10 nm process as having a 64 nm transistor gate pitch and 48 nm interconnect pitch. TSMC reported their 10 nm process as having a 64 nm transistor gate pitch and 42 nm interconnect pitch. Further investigation by Tech Insights revealed these values to be false and they have been updated accordingly. In addition, the transistor fin height of Samsung's 10 nm process was updated by MSSCORPS CO at SEMICON Taiwan 2017. GlobalFoundries decided not to develop a 10 nm node, because it believed it would be short lived. Samsung's 8 nm process is the company's last to exclusively use DUV lithography.

DRAM "10 nm class"

Шаблон:Main For the DRAM industry, the term "10 nm-class" is often used and this dimension generally refers to the half-pitch of the active area.Шаблон:Citation needed The "10 nm" foundry structures are generally much larger.Шаблон:Citation needed

Generally 10 nm class refers to DRAM with a 10-19 nm feature size, and was first introduced Шаблон:Circa. As of 2020 there are three generations of 10 nm class DRAM : 1x nm (19-17 nm, Gen1); 1y nm (16-14 nm, Gen2); and 1z nm (13-11 nm, Gen3). 3rd Generation "1z" DRAM was first introduced Шаблон:Circa by Samsung, and was initially stated to be produced using ArF lithography without the use of EUV lithography; subsequent production did utilise EUV lithography.

Beyond 1z Samsung names its next node (fourth generation 10 nm class) DRAM : "D1a" (for 2021), and beyond that D1b (expected 2022); whilst Micron refers to succeeding "nodes" as "D1α" and "D1β". Micron announced volume shipment of 1α class DRAM in early 2021.