Английская Википедия:Intel iPSC
The Intel Personal SuperComputer (Intel iPSC) was a product line of parallel computers in the 1980s and 1990s. The iPSC/1 was superseded by the Intel iPSC/2, and then the Intel iPSC/860.
iPSC/1
In 1984, Justin Rattner became manager of the Intel Scientific Computers group in Beaverton, Oregon. He hired a team that included mathematician Cleve Moler.[1] The iPSC used a Hypercube internetwork topology of connections between the processors internally inspired by the Caltech Cosmic Cube research project. For that reason, it was configured with nodes numbering with power of two, which correspond to the corners of hypercubes of increasing dimension.[2]
Intel announced the iPSC/1 in 1985, with 32 to 128 nodes connected with Ethernet into a hypercube. The system was managed by a personal computer of the PC/AT era running Xenix, the "cube manager".[3] Each node had a 80286 CPU with 80287 math coprocessor, 512K of RAM, and eight Ethernet ports (seven for the hypercube interconnect, and one to talk to the cube manager).[1]
A message passing interface called NX that was developed by Paul Pierce evolved throughout the life of the iPSC line.[4] Because only the cube manager had connections to the outside world, developing and debugging applications was difficult.[5]
The basic models were the iPSC/d5 (five-dimension hypercube with 32 nodes), iPSC/d6 (six dimensions with 64 nodes), and iPSC/d7 (seven dimensions with 128 nodes). Each cabinet had 32 nodes, and prices ranged up to about half a million dollars for the four-cabinet iPSC/d7 model.[1] Extra memory (iPSC-MX) and vector processor (iPSC-VX) models were also available, in the three sizes. A four-dimensional hypercube was also available (iPSC/d4), with 16 nodes.[6]
iPSC/1 was called the first parallel computer built from commercial off-the-shelf parts.[7] This allowed it to reach the market about the same time as its competitor from nCUBE, even though the nCUBE project had started earlier. Each iPSC cabinet was (overall) 127 cm x 41 cm x 43 cm. Total computer performance was estimated at 2 MFLOPS. Memory width was 16-bit.
Serial #1 iPSC/1 with 32 nodes was delivered to Oak Ridge National Laboratory in 1985.[8][9]
iPSC/2
The Intel iPSC/2 was announced in 1987. It was available in several configurations, the base setup being one cabinet with 16 Intel 80386 processors at 16 MHz, each with 4 MB of memory and a 80387 coprocessor on the same module.[10] The operating system and user programs were loaded from a management PC. This PC was typically an Intel 301 with a special interface card. Instead of Ethernet, a custom Direct-Connect Module with eight channels of about 2.8 Mbyte/s data rate each was used for hypercube interconnection.[10] The custom interconnect hardware resulting in higher cost, but reduced communication delays.[11] The software in the management processor was called the System Resource Manager instead of "cube manager". The system allows for expansion up to 128 nodes, each with processor and coprocessor.[12]
The base modules could be upgraded to the SX (Scalar eXtension) version by adding a Weitek 1167 floating point unit.[13] Another configuration allowed for each processor module to be paired with a VX (Vector eXtension) module with a dedicated multiplication and addition units. This has the downside that the number of available interface card slots is halved. Having multiple cabinets as part of the same iPSC/2 system is necessary to run the maximum number of nodes and allow them to connect to VX modules.[14]
The nodes of iPSC/2 ran the proprietary NX/2 operating system, while the host machine ran System V or Xenix.[15] Nodes could be configured like the iPSC/1 without and local disk storage, or use one of the Direct-Connect Module connections with a clustered file system (called concurrent file system at the time).[14][16] Using both faster node computing elements and the interconnect system improved application performance over the iPSC/1.[17][18] An estimated 140 iPSC/2 systems were built.[19]
iPSC/860
Intel announced the iPSC/860 in 1990. The iPSC/860 consisted of up to 128 processing elements connected in a hypercube, each element consisting of an Intel i860 at 40–50 MHz or Intel 80386 microprocessor.[20] Memory per node was increased to 8 MB and a similar Direct-Connect Module was used, which limited the size to 128 nodes.[21]
One customer was the Oak Ridge National Laboratory.[20] The performance of the iPSC/860 was analyzed in several research projects.[22][23] The iPSC/860 was also the original development platform for the Tachyon parallel ray tracing engine[24][25] that became part of the SPEC MPI 2007 benchmark, and is still widely used today.[26] The iPSC line was superseded by a research project called the Touchstone Delta at the California Institute of Technology which evolved into the Intel Paragon.
References
- ↑ 1,0 1,1 1,2 Шаблон:Cite web
- ↑ Шаблон:Cite web
- ↑ Шаблон:Cite web
- ↑ Шаблон:Cite journal
- ↑ Шаблон:Cite book
- ↑ http://delivery.acm.org/10.1145/70000/63074/p1207-orcutt.pdfШаблон:Dead link
- ↑ Шаблон:Cite web
- ↑ Шаблон:Cite web
- ↑ Шаблон:Cite web
- ↑ 10,0 10,1 Шаблон:Cite web
- ↑ Шаблон:Cite book
- ↑ Шаблон:Cite book
- ↑ Шаблон:Cite book
- ↑ 14,0 14,1 Шаблон:Cite book
- ↑ Шаблон:Cite book
- ↑ Шаблон:Cite book
- ↑ Шаблон:Cite book
- ↑ Шаблон:Cite journal
- ↑ Шаблон:Cite book
- ↑ 20,0 20,1 Шаблон:Cite web
- ↑ Шаблон:Cite book
- ↑ Шаблон:Cite journal
- ↑ Шаблон:Cite journal
- ↑ Шаблон:Cite book
- ↑ Шаблон:Cite thesis
- ↑ Шаблон:Cite book
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