Английская Википедия:CPUID

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Шаблон:Short description Шаблон:Cleanup In the x86 architecture, the CPUID instruction (identified by a CPUID opcode) is a processor supplementary instruction (its name derived from CPU Identification) allowing software to discover details of the processor. It was introduced by Intel in 1993 with the launch of the Pentium and SL-enhanced 486 processors.[1]

A program can use the CPUID to determine processor type and whether features such as MMX/SSE are implemented.

History

Prior to the general availability of the CPUID instruction, programmers would write esoteric machine code which exploited minor differences in CPU behavior in order to determine the processor make and model.[2][3] With the introduction of the 80386 processor, EDX on reset indicated the revision but this was only readable after reset and there was no standard way for applications to read the value.

Outside the x86 family, developers are mostly still required to use esoteric processes (involving instruction timing or CPU fault triggers) to determine the variations in CPU design that are present.

In the Motorola 680x0 family — that never had a CPUID instruction of any kind — certain specific instructions required elevated privileges. These could be used to tell various CPU family members apart. In the Motorola 68010 the instruction MOVE from SR became privileged. This notable instruction (and state machine) change allowed the 68010 to meet the Popek and Goldberg virtualization requirements. Because the 68000 offered an unprivileged MOVE from SR the 2 different CPUs could be told apart by a CPU error condition being triggered.

While the CPUID instruction is specific to the x86 architecture, other architectures (like ARM) often provide on-chip registers which can be read in prescribed ways to obtain the same sorts of information provided by the x86 CPUID instruction.

Calling CPUID

The CPUID opcode is 0F A2.

In assembly language, the CPUID instruction takes no parameters as CPUID implicitly uses the EAX register to determine the main category of information returned. In Intel's more recent terminology, this is called the CPUID leaf. CPUID should be called with EAX = 0 first, as this will store in the EAX register the highest EAX calling parameter (leaf) that the CPU implements.

To obtain extended function information CPUID should be called with the most significant bit of EAX set. To determine the highest extended function calling parameter, call CPUID with EAX = 80000000h.

CPUID leaves greater than 3 but less than 80000000 are accessible only when the model-specific registers have IA32_MISC_ENABLE.BOOT_NT4 [bit 22] = 0 (which is so by default). As the name suggests, Windows NT 4.0 until SP6 did not boot properly unless this bit was set,[4] but later versions of Windows do not need it, so basic leaves greater than 4 can be assumed visible on current Windows systems. Шаблон:As of, basic valid leaves go up to 20h, but the information returned by some leaves are not disclosed in the publicly available documentation, i.e. they are "reserved".

Some of the more recently added leaves also have sub-leaves, which are selected via the ECX register before calling CPUID.

EAX=0: Highest Function Parameter and Manufacturer ID

This returns the CPU's manufacturer ID stringШаблон:Snda twelve-character ASCII string stored in EBX, EDX, ECX (in that order). The highest basic calling parameter (the largest value that EAX can be set to before calling CPUID) is returned in EAX.

Here is a list of processors and the highest function implemented.

Highest Function Parameter
Processors Basic Extended
Earlier Intel 486 CPUID Not Implemented
Later Intel 486 and Pentium 0x01 Not Implemented
Pentium Pro, Pentium II and Celeron 0x02 Not Implemented
Pentium III 0x03 Not Implemented
Pentium 4 0x02 0x8000 0004
Xeon 0x02 0x8000 0004
Pentium M 0x02 0x8000 0004
Pentium 4 with Hyper-Threading 0x05 0x8000 0008
Pentium D (8xx) 0x05 0x8000 0008
Pentium D (9xx) 0x06 0x8000 0008
Core Duo 0x0A 0x8000 0008
Core 2 Duo 0x0A 0x8000 0008
Xeon 3000, 5100, 5200, 5300, 5400 (5000 series) 0x0A 0x8000 0008
Core 2 Duo 8000 series 0x0D 0x8000 0008
Xeon 5200, 5400 series 0x0A 0x8000 0008
Atom 0x0A 0x8000 0008
Nehalem-based processors 0x0B 0x8000 0008
Ivy Bridge-based processors 0x0D 0x8000 0008
Skylake-based processors (proc base & max freq; Bus ref. freq) 0x16 0x8000 0008
System-On-Chip Vendor Attribute Enumeration Main Leaf 0x17 0x8000 0008

The following are known processor manufacturer ID strings:

The following are ID strings used by open source soft CPU cores:

The following are known ID strings from virtual machines:

For instance, on a GenuineIntel processor values returned in EBX is 0x756e6547, EDX is 0x49656e69 and ECX is 0x6c65746e. The following example code displays the vendor ID string as well as the highest calling parameter that the CPU implements. 

	.intel_syntax noprefix
	.text
.m0: .string "CPUID: %x\n"
.m1: .string "Largest basic function number implemented: %i\n"
.m2: .string "Vendor ID: %s\n"

    .globl main

main:
	push    r12
	mov	    eax, 1
	sub	    rsp, 16
    cpuid
    lea	    rdi, .m0[rip]
	mov	    esi, eax
	call	printf
	mov     eax, 0
    cpuid
	lea	    rdi, .m1[rip]
	mov	    esi, eax
	mov	    r12d, edx
	mov	    ebp, ecx
	call    printf
	mov     3[rsp], ebx
	lea	    rsi, 3[rsp]
    lea	    rdi, .m2[rip]
    mov     7[rsp], r12d
    mov     11[rsp], ebp
	call	printf
	add	    rsp, 16
	pop	    r12
	ret

    .section .note.GNU-stack,"",@progbits

On some processors, it is possible to modify the Manufacturer ID string reported by CPUID.(EAX=0) by writing a new ID string to particular MSRs (Model-specific registers) using the WRMSR instruction. This has been used on non-Intel processors to enable features and optimizations that have been disabled in software for CPUs that don't return the GenuineIntel ID string.[14] Processors that are known to possess such MSRs include:

Processors with Manufacturer ID MSRs
Processor MSRs
IDT WinChip 108h-109h[15]
VIA C3, C7 1108h-1109h[16]
VIA Nano 1206h-1207h[17]
Transmeta Crusoe 80860001h-80860003h[18]
AMD Geode GX, LX 3000h-3001h[19]
DM&P Vortex86EX2 52444300h-52444301h[20]

EAX=1: Processor Info and Feature Bits

This returns the CPU's stepping, model, and family information in register EAX (also called the signature of a CPU), feature flags in registers EDX and ECX, and additional feature info in register EBX.[21]

CPUID EAX=1: Processor Version Information in EAX
EAX
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved Extended Family ID Extended Model ID Reserved Processor Type Family ID Model Stepping ID
  • Stepping ID is a product revision number assigned due to fixed errata or other changes.
  • The actual processor model is derived from the Model, Extended Model ID and Family ID fields. If the Family ID field is either 6 or 15, the model is equal to the sum of the Extended Model ID field shifted left by 4 bits and the Model field. Otherwise, the model is equal to the value of the Model field.
  • The actual processor family is derived from the Family ID and Extended Family ID fields. If the Family ID field is equal to 15, the family is equal to the sum of the Extended Family ID and the Family ID fields. Otherwise, the family is equal to the value of the Family ID field.
  • The meaning of the Processor Type field is given in the table below.
Processor Type
Type Encoding in Binary
Original equipment manufacturer (OEM) Processor 00
Intel Overdrive Processor 01
Dual processor (applicable to Intel P5 Pentium processors only)[22] 10
Reserved value 11

Шаблон:Vpad

As of October 2023, the following x86 processor family IDs are known:[23]

CPUID EAX=1: Processor Family IDs
Family ID +
Extended Family ID		 Intel AMD Other
0h Шаблон:N/a Шаблон:N/a Шаблон:N/a
1h Шаблон:N/a Шаблон:N/a Шаблон:N/a
2h Шаблон:N/a Шаблон:N/a Шаблон:N/a
3h Шаблон:N/a Шаблон:N/a Шаблон:N/a
4h 486 486,[24]
5x86,
Élan SC4xx/5xx[25] 		Cyrix 5x86,[26]
Cyrix MediaGX,[27]
UMC Green CPU,[28]
MCST Elbrus (most models),[7]
MiSTer ao486[29]
5h Pentium,
Pentium MMX,
Quark X1000 		K5,
K6 		Cyrix 6x86,
Cyrix MediaGXm,[27]
Geode (except NX),
NexGen Nx586,[28]
IDT WinChip,
Transmeta Crusoe,
Rise mP6,
SiS 550,
DM&P Vortex86 (early),[30]
RDC IAD 100,
MCST Elbrus-8C2[7]
6h Pentium Pro,
Pentium II,
Pentium III,
Pentium M,
Шаблон:Nowrap
Шаблон:Nowrap
Xeon (except NetBurst variants),
Xeon Phi (except KNC) 		K7: Athlon,
Athlon XP 		Cyrix 6x86MX/MII,
VIA C3,
VIA C7,
VIA Nano,
DM&P Vortex86 (DX3,EX2[31]),
Zhaoxin ZX-A/B/C/C+,
(Centaur CNS[32]),
MCST Elbrus-12C/16C/2C3[7]
7h Itanium
(in IA-32 mode) 		Шаблон:N/a Zhaoxin KaiXian,
Zhaoxin KaisHeng
8h Шаблон:N/a Шаблон:N/a Шаблон:N/a
9h Шаблон:N/a Шаблон:N/a Шаблон:N/a
0Ah Шаблон:N/a Шаблон:N/a Шаблон:N/a
0Bh Xeon Phi (Knights Corner)[33] Шаблон:N/a Шаблон:N/a
0Ch Шаблон:N/a Шаблон:N/a Шаблон:N/a
0Dh Шаблон:N/a Шаблон:N/a Шаблон:N/a
0Eh Шаблон:N/a Шаблон:N/a Шаблон:N/a
0Fh NetBurst (Pentium 4) K8/Hammer
(Athlon 64) 		Transmeta Efficeon
10h Шаблон:N/a K10: Phenom Шаблон:N/a
11h Itanium 2[34]
(in IA-32 mode)		 Turion X2 Шаблон:N/a
12h Шаблон:N/a Llano Шаблон:N/a
13h Шаблон:N/a Шаблон:N/a Шаблон:N/a
14h Шаблон:N/a Bobcat Шаблон:N/a
15h Шаблон:N/a Bulldozer,
Piledriver,
Steamroller,
Excavator		 Шаблон:N/a
16h Шаблон:N/a Jaguar,
Puma		 Шаблон:N/a
17h Шаблон:N/a Zen 1,
Zen 2		 Шаблон:N/a
18h Шаблон:N/a Hygon Dhyana
19h Шаблон:N/a Zen 3,
Zen 4		 Шаблон:N/a
1Ah Шаблон:N/a (Zen 5) Шаблон:N/a

Шаблон:Notelist

Шаблон:Vpad

CPUID EAX=1: Additional Information in EBX
Bits EBX Valid
7:0 Brand Index
15:8 CLFLUSH line size (Value * 8 = cache line size in bytes) if CLFLUSH feature flag is set.

CPUID.01.EDX.CLFSH [bit 19]= 1

23:16 Maximum number of addressable IDs for logical processors in this physical package;

The nearest power-of-2 integer that is not smaller than this value is the number of unique initial APIC IDs reserved for addressing different logical processors in a physical package.

Former use: Number of logical processors per physical processor; two for the Pentium 4 processor with Hyper-Threading Technology.[35]

if Hyper-threading feature flag is set.

CPUID.01.EDX.HTT [bit 28]= 1

31:24 Local APIC ID: The initial APIC-ID is used to identify the executing logical processor.

It can also be identified via the cpuid 0BH leaf ( CPUID.0Bh.EDX[x2APIC-ID] ).

Pentium 4 and subsequent processors.

The processor info and feature flags are manufacturer specific but usually, the Intel values are used by other manufacturers for the sake of compatibility.

CPUID EAX=1: Feature Information in EDX and ECX
EDX ECXШаблон:Efn
Bit Short Feature Short Feature Bit
0 fpu Onboard x87 FPU sse3 SSE3 (Prescott New Instructions - PNI) 0
1 vme Virtual 8086 mode extensions (such as VIF, VIP, PVI) pclmulqdq PCLMULQDQ (carry-less multiply) instruction 1
2 de Debugging extensions (CR4 bit 3) dtes64 64-bit debug store (edx bit 21) 2
3 pse Page Size Extension (4 MByte pages) monitor MONITOR and MWAIT instructions (PNI) 3
4 tsc Time Stamp Counter and RDTSC instruction ds-cpl CPL qualified debug store 4
5 msr Model-specific registers and RDMSR/WRMSR instructions vmx Virtual Machine eXtensions 5
6 pae Physical Address Extension smx Safer Mode Extensions (LaGrande) (GETSEC instruction) 6
7 mce Machine Check Exception est Enhanced SpeedStep 7
8 cx8Шаблон:Efn CMPXCHG8B (compare-and-swap) instruction tm2 Thermal Monitor 2 8
9 apicШаблон:Efn Onboard Advanced Programmable Interrupt Controller ssse3 Supplemental SSE3 instructions 9
10 (mtrr)Шаблон:Efn (reserved) cnxt-id L1 Context ID 10
11 sepШаблон:Efn SYSENTER and SYSEXIT fast system call instructions sdbg Silicon Debug interface 11
12 mtrr Memory Type Range Registers fma Fused multiply-add (FMA3) 12
13 pge Page Global Enable bit in CR4 cx16 CMPXCHG16B instruction 13
14 mca Machine check architecture xtpr Can disable sending task priority messages 14
15 cmov Conditional move: CMOV, FCMOV and FCOMI instructionsШаблон:Efn pdcm Perfmon & debug capability 15
16 pat Page Attribute Table (reserved)Шаблон:Efn 16
17 pse-36 36-bit page size extension pcid Process context identifiers (CR4 bit 17) 17
18 psn Processor Serial Number supported and enabledШаблон:Efn dca Direct cache access for DMA writes[36][37] 18
19 clfsh CLFLUSH cache line flush instruction (SSE2) sse4.1 SSE4.1 instructions 19
20 (nx) No-execute (NX) bit (Itanium only)[38]Шаблон:Efn sse4.2 SSE4.2 instructions 20
21 ds Debug store: save trace of executed jumps x2apic x2APIC (enhanced APIC) 21
22 acpi Onboard thermal control MSRs for ACPI movbe MOVBE instruction (big-endian) 22
23 mmx MMX instructions (64-bit SIMD) popcnt POPCNT instruction 23
24 fxsr FXSAVE, FXRSTOR instructions, CR4 bit 9 tsc-deadline APIC implements one-shot operation using a TSC deadline value 24
25 sse Streaming SIMD Extensions (SSE) instructions
(aka "Katmai New Instructions"; 128-bit SIMD) 		aes-ni AES instruction set 25
26 sse2 SSE2 instructions xsave Extensible processor state save/restore:
XSAVE, XRSTOR, XSETBV, XGETBV instructions 		26
27 ss CPU cache implements self-snoop osxsave XSAVE enabled by OS 27
28 htt Max APIC IDs reserved field is ValidШаблон:Efn avx Advanced Vector Extensions (256-bit SIMD) 28
29 tm Thermal monitor automatically limits temperature f16c Floating-point conversion instructions to/from FP16 format 29
30 ia64 IA64 processor emulating x86[38] rdrnd RDRAND (on-chip random number generator) feature 30
31 pbe Pending Break Enable (PBE# pin) wakeup capability hypervisor Hypervisor present (always zero on physical CPUs)[39][40][41] 31

Шаблон:Notelist Reserved fields should be masked before using them for processor identification purposes.

EAX=2: Cache and TLB Descriptor information

This returns a list of descriptors indicating cache and TLB capabilities in EAX, EBX, ECX and EDX registers.

On processors that support this leaf, calling CPUID with EAX=2 will cause the bottom byte of EAX to be set to 01h and the remaining 15 bytes of EAX/EBX/ECX/EDX to be filled with 15 descriptors, one byte each. These descriptors provide information about the processor's caches, TLBs and prefetch. This is typically one cache or TLB per descriptor, but some descriptor-values provide other information as well - in particular, 00h is used for an empty descriptor, FFh indicates that the leaf does not contain valid cache information and that leaf 4h should be used instead, and FEh indicates that the leaf does not contain valid TLB information and that leaf 18h should be used instead. The descriptors may appear in any order.

For each of the four registers (EAX,EBX,ECX,EDX), if bit 31 is set, then the register should not be considered to contain valid descriptors (e.g. on Itanium in IA-32 mode, CPUID(EAX=2) returns 80000000h in EDX - this should be interpreted to mean that EDX contains no valid information, not that it contains a 512K L2 cache.) Шаблон:Vpad The table below provides, for known descriptor values, a condensed description of the cache or TLB indicated by that descriptor value (or other information, where that applies). The suffixes used in the table are:

  • K,M,G : binary kilobyte, megabyte, gigabyte (capacity for caches, page-size for TLBs)
  • E : entries (for TLBs; e.g. 64E = 64 entries)
  • p : page-size (e.g. 4Kp for TLBs where each entry describes one 4KByte page, 4K/2Mp for TLBs where each entry can describe either one 4Kbyte page or one 2MByte hugepage)
  • L : cache-line size (e.g. 32L = 32-byte cache line size)
  • S : cache sector size (e.g. 2S means that the cache uses sectors of 2 cache-lines each)
  • A : associativity (e.g. 6A = 6-way set-associative, FA = fully-associative)
Legend for cache/TLB descriptor byte encodings
Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Yes (reserved)
CPUID EAX=2: Cache/TLB descriptor byte encodings
x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF
0x Шаблон:Yes Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade 0x Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade 0x
1x Шаблон:Shade Шаблон:Shade 1x Шаблон:Shade Шаблон:Shade 1x
2x Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade (128-byte
prefetch)Шаблон:Efn		 (128-byte
prefetch)Шаблон:Efn 		2x (128-byte
prefetch)Шаблон:Efn		 Шаблон:Shade Шаблон:Shade 2x
3x Шаблон:Shade 3x Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade 3x
4x Шаблон:Yes Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade 4x Шаблон:Shade L2C/L3C:Шаблон:Efn
4M, 16A, 64L 		Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade 4x
5x Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade 5x Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade 5x
6x Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade 6x Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade 6x
7x Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade 7x Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade 7x
8x Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade 8x Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade 8x
9x Шаблон:Shade Шаблон:Shade 9x Шаблон:Shade 9x
Ax Шаблон:Shade Ax Ax
Bx Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Bx Шаблон:Shade Bx
Cx Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Cx Шаблон:Shade Cx
Dx Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Dx Шаблон:Shade Шаблон:Shade Шаблон:Shade Шаблон:Shade Dx
Ex Шаблон:Shade Шаблон:Shade Шаблон:Shade Ex Шаблон:Shade Шаблон:Shade Шаблон:Shade Ex
Fx Шаблон:Yes Шаблон:Yes Fx Шаблон:Yes Шаблон:Yes Fx
x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF

Шаблон:Notelist Шаблон:Vpad

EAX=3: Processor Serial Number

Шаблон:See also This returns the processor's serial number. The processor serial number was introduced on Intel Pentium III, but due to privacy concerns, this feature is no longer implemented on later models (the PSN feature bit is always cleared). Transmeta's Efficeon and Crusoe processors also provide this feature. AMD CPUs however, do not implement this feature in any CPU models.

For Intel Pentium III CPUs, the serial number is returned in the EDX:ECX registers. For Transmeta Efficeon CPUs, it is returned in the EBX:EAX registers. And for Transmeta Crusoe CPUs, it is returned in the EBX register only.

Note that the processor serial number feature must be enabled in the BIOS setting in order to function.

EAX=4 and EAX=Bh: Intel thread/core and cache topology

These two leaves are used for processor topology (thread, core, package) and cache hierarchy enumeration in Intel multi-core (and hyperthreaded) processors.[42] Шаблон:As of AMD does not use these leaves but has alternate ways of doing the core enumeration.[43]

Unlike most other CPUID leaves, leaf Bh will return different values in EDX depending on which logical processor the CPUID instruction runs; the value returned in EDX is actually the x2APIC id of the logical processor. The x2APIC id space is not continuously mapped to logical processors, however; there can be gaps in the mapping, meaning that some intermediate x2APIC ids don't necessarily correspond to any logical processor. Additional information for mapping the x2APIC ids to cores is provided in the other registers. Although the leaf Bh has sub-leaves (selected by ECX as described further below), the value returned in EDX is only affected by the logical processor on which the instruction is running but not by the subleaf.

The processor(s) topology exposed by leaf Bh is a hierarchical one, but with the strange caveat that the order of (logical) levels in this hierarchy doesn't necessarily correspond to the order in the physical hierarchy (SMT/core/package). However, every logical level can be queried as an ECX subleaf (of the Bh leaf) for its correspondence to a "level type", which can be either SMT, core, or "invalid". The level id space starts at 0 and is continuous, meaning that if a level id is invalid, all higher level ids will also be invalid. The level type is returned in bits 15:08 of ECX, while the number of logical processors at the level queried is returned in EBX. Finally, the connection between these levels and x2APIC ids is returned in EAX[4:0] as the number of bits that the x2APIC id must be shifted in order to obtain a unique id at the next level.

As an example, a dual-core Westmere processor capable of hyperthreading (thus having two cores and four threads in total) could have x2APIC ids 0, 1, 4 and 5 for its four logical processors. Leaf Bh (=EAX), subleaf 0 (=ECX) of CPUID could for instance return 100h in ECX, meaning that level 0 describes the SMT (hyperthreading) layer, and return 2 in EBX because there are two logical processors (SMT units) per physical core. The value returned in EAX for this 0-subleaf should be 1 in this case, because shifting the aforementioned x2APIC ids to the right by one bit gives a unique core number (at the next level of the level id hierarchy) and erases the SMT id bit inside each core. A simpler way to interpret this information is that the last bit (bit number 0) of the x2APIC id identifies the SMT/hyperthreading unit inside each core in our example. Advancing to subleaf 1 (by making another call to CPUID with EAX=Bh and ECX=1) could for instance return 201h in ECX, meaning that this is a core-type level, and 4 in EBX because there are 4 logical processors in the package; EAX returned could be any value greater than 3, because it so happens that bit number 2 is used to identify the core in the x2APIC id. Note that bit number 1 of the x2APIC id is not used in this example. However, EAX returned at this level could well be 4 (and it happens to be so on a Clarkdale Core i3 5x0) because that also gives a unique id at the package level (=0 obviously) when shifting the x2APIC id by 4 bits. Finally, you may wonder what the EAX=4 leaf can tell us that we didn't find out already. In EAX[31:26] it returns the APIC mask bits reserved for a package; that would be 111b in our example because bits 0 to 2 are used for identifying logical processors inside this package, but bit 1 is also reserved although not used as part of the logical processor identification scheme. In other words, APIC ids 0 to 7 are reserved for the package, even though half of these values don't map to a logical processor.

The cache hierarchy of the processor is explored by looking at the sub-leaves of leaf 4. The APIC ids are also used in this hierarchy to convey information about how the different levels of cache are shared by the SMT units and cores. To continue our example, the L2 cache, which is shared by SMT units of the same core but not between physical cores on the Westmere is indicated by EAX[26:14] being set to 1, while the information that the L3 cache is shared by the whole package is indicated by setting those bits to (at least) 111b. The cache details, including cache type, size, and associativity are communicated via the other registers on leaf 4.

Beware that older versions of the Intel app note 485 contain some misleading information, particularly with respect to identifying and counting cores in a multi-core processor;[44] errors from misinterpreting this information have even been incorporated in the Microsoft sample code for using CPUID, even for the 2013 edition of Visual Studio,[45] and also in the sandpile.org page for CPUID,[46] but the Intel code sample for identifying processor topology[42] has the correct interpretation, and the current Intel Software Developer's Manual has a more clear language. The (open source) cross-platform production code[47] from Wildfire Games also implements the correct interpretation of the Intel documentation.

Topology detection examples involving older (pre-2010) Intel processors that lack x2APIC (thus don't implement the EAX=Bh leaf) are given in a 2010 Intel presentation.[48] Beware that using that older detection method on 2010 and newer Intel processors may overestimate the number of cores and logical processors because the old detection method assumes there are no gaps in the APIC id space, and this assumption is violated by some newer processors (starting with the Core i3 5x0 series), but these newer processors also come with an x2APIC, so their topology can be correctly determined using the EAX=Bh leaf method.

EAX=6: Thermal and power management

This returns feature bits in the EAX register and additional information in the EBX, ECX and EDX registers.

CPUID EAX=6: Thermal/power management feature bits in EAX
Bit EAX
Short Feature
0 DTS Digital Thermal Sensor capability
1 Intel Turbo Boost Technology capability
2 ARATШаблон:Efn Always Running APIC Timer capability
3 (reserved)
4 PLN Power Limit Notification capability
5 ECMD Extended Clock Modulation Duty capability
6 PTM Package Thermal Management capability
7 HWP Hardware-controlled Performance States. MSRs added:
  • IA32_PM_ENABLE(770h)
  • IA32_HWP_CAPABILITIES(771h)
  • IA32_HWP_REQUEST(774h)
  • IA32_HWP_STATUS(777h
8 HWP_Notification HWP notification of dynamic guaranteed performance change - IA32_HWP_INTERRUPT(773h) MSR
9 HWP_Activity_­Window HWP Activity Window control - bits 41:32 of IA32_HWP_REQUEST MSR
10 HWP_Energy_­Performance_­Preference HWP Energy/performance preference control - bits 31:24 of IA32_HWP_REQUEST MSR
11 HWP_Package_­Level_Request HWP Package-level control - IA32_HWP_REQUEST_PKG(772h) MSR
12 (reserved)
13 HDC Hardware Duty Cycling supported. MSRs added:
  • IA32_PKG_HDC_CTL (DB0h)
  • IA32_PM_CTL1 (DB1h)
  • IA32_THREAD_STALL (DB2h)
14 Intel Turbo Boost Max Technology 3.0 available
15 Interrupts upon changes to IA32_HWP_CAPABILITIES.Highest_Performance (bits 7:0) supported
16 HWP PECI override supported - bits 63:60 of IA32_HWP_PECI_REQUEST_INFO(775h) MSR
17 Flexible HWP - bits 63:59 of IA32_HWP_REQUEST MSR
18 Fast access mode for IA32_HWP_REQUEST MSR supportedШаблон:Efn
19 HW_FEEDBACK Hardware Feedback Interface. Added MSRs:
  • IA32_HW_FEEDBACK_PTR(17D0h)
  • IA32_HW_FEEDBACK_CONFIG(17D1h) (bit 0 enables HFI, bit 1 enables Intel Thread Director)
20 IA32_HWP_REQUEST of idle logical processor ignored when only one of two logical processors that share a physical processor is active.
21 (reserved)
22 IA32_HWP_CTL(776h) MSR supported[49]
23 Intel Thread Director supported. Added MSRs:
  • IA32_THREAD_FEEDBACK_CHAR(17D2h)
  • IA32_HW_FEEDBACK_THREAD_CONFIG(17D4h)
24 IA32_THERM_INTERRUPT MSR bit 25 supported

31:25
  		(reserved)

Шаблон:Notelist

CPUID EAX=6: Thermal/power management feature fields in EBX, ECX and EDX
Bit EBX ECX EDX Bit
0 Number of Interrupt Thresholds in Digital Thermal Sensor Effective frequency interface supported - IA32_MPERF(0E7h) and IA32_APERF(0E8h) MSRs Hardware Feedback reporting: Performance Capability Reporting supported 0
1 (ACNT2 Capability)Шаблон:Efn Hardware Feedback reporting: Efficiency Capability Reporting supported 1
2 (reserved) (reserved) 2
3 Performance-Energy Bias capability - IA32_ENERGY_PERF_BIAS(1B0h) MSR 3
7:4 (reserved) (reserved) 7:4
11:8 Number of Intel Thread Director classes supported by hardware Size of Hardware Feedback interface structure (in units of 4 Kbytes) minus 1 11:8
15:12 (reserved) 15:12

31:16
  		(reserved) Index of this logical processor's row in hardware feedback interface structure
31:16
 

Шаблон:Notelist Шаблон:Vpad

EAX=7, ECX=0: Extended Features

This returns extended feature flags in EBX, ECX, and EDX. Returns the maximum ECX value for EAX=7 in EAX.

CPUID EAX=7,ECX=0: Extended feature bits in EBX, ECX and EDX
Bit EBX ECX EDX Bit
Short Feature Short Feature Short Feature
0 fsgsbase Access to base of %fs and %gs prefetchwt1 PREFETCHWT1 instruction sgx-tem ? 0
1 IA32_TSC_ADJUST MSR avx512-vbmi AVX-512 Vector Bit Manipulation Instructions sgx-keys Attestation Services for Intel SGX 1
2 sgx Software Guard Extensions umip User-mode Instruction Prevention avx512-4vnniw AVX-512 4-register Neural Network Instructions 2
3 bmi1 Bit Manipulation Instruction Set 1 pku Memory Protection Keys for User-mode pages avx512-4fmaps AVX-512 4-register Multiply Accumulation Single precision 3
4 hle TSX Hardware Lock Elision ospke PKU enabled by OS fsrm Fast Short Шаблон:Nowrap 4
5 avx2 Advanced Vector Extensions 2 waitpkg Timed pause and user-level monitor/wait instructions (TPAUSE, UMONITOR, UMWAIT) uintr User Inter-processor Interrupts 5
6 fdp-excptn-only x87 FPU data pointer register updated on exceptions only avx512-vbmi2 AVX-512 Vector Bit Manipulation Instructions 2 (reserved) 6
7 smep Supervisor Mode Execution Prevention cet_ss/shstk Control flow enforcement (CET): shadow stack (SHSTK alternative name) (reserved) 7
8 bmi2 Bit Manipulation Instruction Set 2 gfni Galois Field instructions avx512-vp2intersect AVX-512 vector intersection instructions on 32/64-bit integers 8
9 erms Enhanced Шаблон:Nowrap vaes Vector AES instruction set (VEX-256/EVEX) srbds-ctrl Special Register Buffer Data Sampling Mitigations 9
10 invpcid INVPCID instruction vpclmulqdq CLMUL instruction set (VEX-256/EVEX) md-clear VERW instruction clears CPU buffers 10
11 rtm TSX Restricted Transactional Memory avx512-vnni AVX-512 Vector Neural Network Instructions rtm-always-abort All TSX transactions are aborted 11
12 rdt-m/pqm Intel Resource Director (RDT) Monitoring or AMD Platform QOS Monitoring avx512-bitalg AVX-512 BITALG instructions (reserved) 12
13 x87 FPU CS and DS deprecated tme_en Total Memory Encryption MSRs available TSX_FORCE_ABORT MSR is available 13
14 mpx Intel MPX (Memory Protection Extensions) avx512-vpopcntdq AVX-512 Vector Population Count Double and Quad-word serialize SERIALIZE instruction 14
15 rdt-a/pqe Intel Resource Director (RDT) Allocation or AMD Platform QOS Enforcement fzm ? hybrid Mixture of CPU types in processor topology (e.g. Alder Lake) 15
16 avx512-f AVX-512 Foundation la57 5-level paging (57 address bits) tsxldtrk TSX load address tracking suspend/resume instructions (TSUSLDTRK and TRESLDTRK) 16
17 avx512-dq AVX-512 Doubleword and Quadword Instructions mawau The value of userspace MPX Address-Width Adjust used by the BNDLDX and BNDSTX Intel MPX instructions in 64-bit mode (reserved) 17
18 rdseed RDSEED instruction pconfig Platform configuration (Memory Encryption Technologies Instructions) 18
19 adx Intel ADX (Multi-Precision Add-Carry Instruction Extensions) lbr Architectural Last Branch Records 19
20 smap Supervisor Mode Access Prevention cet-ibt Control flow enforcement (CET): indirect branch tracking 20
21 avx512-ifma AVX-512 Integer Fused Multiply-Add Instructions (reserved) 21
22 (pcommit) (PCOMMIT instruction, deprecated)[50] rdpid RDPID (Read Processor ID) instruction and IA32_TSC_AUX MSR amx-bf16 AMX tile computation on bfloat16 numbers 22
23 clflushopt CLFLUSHOPT instruction kl AES Key Locker avx512-fp16 AVX-512 half-precision floating-point arithmetic instructions[51] 23
24 clwb CLWB (Cache line writeback) instruction bus-lock-detect Bus lock debug exceptions amx-tile AMX tile load/store instructions 24
25 pt Intel Processor Trace cldemote CLDEMOTE (Cache line demote) instruction amx-int8 AMX tile computation on 8-bit integers 25
26 avx512-pf AVX-512 Prefetch Instructions mprr ? ibrs / spec_ctrl Speculation Control, part of Indirect Branch Control (IBC):
Indirect Branch Restricted Speculation (IBRS) and
Indirect Branch Prediction Barrier (IBPB)[52][53] 		26
27 avx512-er AVX-512 Exponential and Reciprocal Instructions movdiri MOVDIRI instruction stibp Single Thread Indirect Branch Predictor, part of IBC[52] 27
28 avx512-cd AVX-512 Conflict Detection Instructions movdir64b MOVDIR64B (64-byte direct store) instruction L1D_FLUSH IA32_FLUSH_CMD MSR 28
29 sha SHA-1 and SHA-256 extensions enqcmd Enqueue Stores and EMQCMD/EMQCMDS instructions IA32_ARCH_CAPABILITIES MSR (lists speculative side channel mitigations[52]) 29
30 avx512-bw AVX-512 Byte and Word Instructions sgx-lc SGX Launch Configuration IA32_CORE_CAPABILITIES MSR (lists model-specific core capabilities) 30
31 avx512-vl AVX-512 Vector Length Extensions pks Protection keys for supervisor-mode pages ssbd Speculative Store Bypass Disable,[52] as mitigation for Speculative Store Bypass (IA32_SPEC_CTRL) 31

EAX=7, ECX=1: Extended Features

This returns extended feature flags in all four registers.

CPUID EAX=7,ECX=1: Extended feature bits in EAX, EBX, ECX, and EDX
Bit EAX EBX ECX EDX Bit
Short Feature Short Feature Short Feature Short Feature
0 sha512 SHA-512 extensions Intel PPIN (Protected Processor Inventory Number): IA32_PPIN_CTL (04Eh) and IA32_PPIN (04Fh) MSRs. (reserved) (reserved) 0
1 sm3 SM3 hash extensions pbndkb Total Storage Encryption: PBNDKB instruction and TSE_CAPABILITY (9F1h) MSR. (reserved) (reserved) 1
2 sm4 SM4 cipher extensions (reserved) legacy_reduced_isa X86S (reserved) 2
3 rao-int Remote Atomic Operations on integers: AADD, AAND, AOR, AXOR instructions (reserved) (reserved) (reserved) 3
4 avx-vnni AVX Vector Neural Network Instructions (VNNI) (VEX encoded) (reserved) sipi64 64-bit SIPI avx-vnni-int8 AVX VNNI INT8 instructions 4
5 avx512-bf16 AVX-512 instructions for bfloat16 numbers (reserved) (reserved) avx-ne-convert AVX no-exception FP conversion instructions (bfloat16↔FP32 and FP16→FP32) 5
6 lass Linear Address Space Separation (CR4 bit 27) (reserved) (reserved) (reserved) 6
7 cmpccxadd CMPccXADD instructions (reserved) (reserved) (reserved) 7
8 archperfmonext Architectural Performance Monitoring Extended Leaf (EAX=23h) (reserved) (reserved) amx-complex AMX support for "complex" tiles (TCMMIMFP16PS and TCMMRLFP16PS) 8
9 dedup ? (reserved) (reserved) (reserved) 9
10 fzrm Fast zero-length Шаблон:Nowrap (reserved) (reserved) avx-vnni-int16 AVX VNNI INT16 instructions 10
11 fsrs Fast short Шаблон:Nowrap (reserved) (reserved) (reserved) 11
12 rsrcs Fast short Шаблон:Nowrap and Шаблон:Nowrap (reserved) (reserved) (reserved) 12
13 (reserved) (reserved) (reserved) (reserved) 13
14 (reserved) (reserved) (reserved) prefetchi Instruction-cache prefetch instructions (PREFETCHIT0 and PREFETCHIT1) 14
15 (reserved) (reserved) (reserved) user_msr User-mode MSR access instructions (URDMSR and UWRMSR) 15
16 (reserved) (reserved) (reserved) (reserved) 16
17 fred Flexible Return and Event Delivery[54] (reserved) (reserved) uiret-uif-from-rflags If 1, the UIRET (User Interrupt Return) instruction will set UIF (User Interrupt Flag) to the value of bit 1 of the RFLAGS image popped off the stack. 17
18 lkgs LKGS Instruction[54] (reserved) (reserved) cet-sss If 1, then Control-Flow Enforcement (CET) Supervisor Shadow Stacks (SSS) are guaranteed not to become prematurely busy as long as shadow stack switching does not cause page faults on the stack being switched to.[55][56] 18
19 wrmsrns WRMSRNS instruction (non-serializing write to MSRs) (reserved) (reserved) avx10 AVX10 Converged Vector ISA (see also leaf 24h)[57] 19
20 nmi_src NMI source reporting[54] (reserved) (reserved) (reserved) 20
21 amx-fp16 AMX instructions for FP16 numbers (reserved) (reserved) APX_F Advanced Performance Extensions, Foundation (adds REX2 and extended EVEX prefix encodings to support 32 GPRs, as well as some new instructions)[58] 21
22 hreset HRESET instruction, IA32_HRESET_ENABLE (17DAh) MSR, and Processor History Reset Leaf (EAX=20h) (reserved) (reserved) (reserved) 22
23 avx-ifma AVX IFMA instructions (reserved) (reserved) (reserved) 23
24 (reserved) (reserved) (reserved) (reserved) 24
25 (reserved) (reserved) (reserved) (reserved) 25
26 lam Linear Address Masking (reserved) (reserved) (reserved) 26
27 msrlist RDMSRLIST and WRMSRLIST instructions, and the IA32_BARRIER (02Fh) MSR (reserved) (reserved) (reserved) 27
28 (reserved) (reserved) (reserved) (reserved) 28
29 (reserved) (reserved) (reserved) (reserved) 29
30 invd_disable_­post_bios_done If 1, supports INVD instruction execution prevention after BIOS Done. (reserved) (reserved) (reserved) 30
31 (reserved) (reserved) (reserved) (reserved) 31

EAX=7, ECX=2: Extended Features

This returns extended feature flags in EDX.

EAX, EBX and ECX are reserved.

CPUID EAX=7,ECX=2: Extended feature bits in EDX
Bit EDX
Short Feature
0 psfd Fast Store Forwarding Predictor disable supported. (SPEC_CTRL (MSR 48h) bit 7)
1 ipred_ctrl IPRED_DIS controls[59] supported. (SPEC_CTRL bits 3 and 4)

IPRED_DIS prevents instructions at an indirect branch target from speculatively executing until the branch target address is resolved.

2 rrsba_ctrl RRSBA behavior[60][59] disable supported. (SPEC_CTRL bits 5 and 6)
3 ddpd_u Data Dependent Prefetcher disable supported. (SPEC_CTRL bit 8)
4 bhi_ctrl BHI_DIS_S behavior[59] enable supported. (SPEC_CTRL bit 10)

BHI_DIS_S prevents predicted targets of indirect branches executed in ring0/1/2 from being selected based on branch history from branches executed in ring 3.

5 mcdt_no If set, the processor does not exhibit MXCSR configuration dependent timing.
6 UC-lock disable feature supported.

31:7
  		(reserved)

Шаблон:Vpad

EAX=0Dh: XSAVE features and state-components

This leaf is used to enumerate XSAVE features and state-components.

The XSAVE instruction set extension is designed to save/restore CPU extended state (typically for the purpose of context switching) in a manner that can be extended to cover new instruction set extensions without the OS context-switching code needing to understand the specifics of the new extensions. This is done by defining a series of state-components, each with a size and offset within a given save area, and each corresponding to a subset of the state needed for one CPU extension or another. The EAX=0Dh CPUID leaf is used to provide information about which state-components the CPU supports and what their sizes/offsets are, so that the OS can reserve the proper amount of space and set the associated enable-bits.

The state-components can be subdivided into two groups: user-state (state-items that are visible to the application, e.g. AVX-512 vector registers), and supervisor-state (state items that affect the application but are not directly user-visible, e.g. user-mode interrupt configuration). The user-state items are enabled by setting their associated bits in the XCR0 control register, while the supervisor-state items are enabled by setting their associated bits in the IA32_XSS (0DA0h) MSR - the indicated state items then become the state-components that can be saved and restored with the XSAVE/XRSTOR family of instructions. Шаблон:Vpad The XSAVE mechanism can handle up to 63 state-components in this manner. State-components 0 and 1 (x87 and SSE, respectively) have fixed offsets and sizes - for state-components 2 to 62, their sizes, offsets and a few additional flags can be queried by executing CPUID with EAX=0Dh and ECX set to the index of the state-component. This will return the following items in EAX, EBX and ECX (with EDX being reserved):

CPUID EAX=0Dh, ECX≥2: XSAVE state-component information
Bit EAX EBX ECX Bit
0 Size in bytes of state-component Offset of state-component from the start of the XSAVE/XRSTOR save area

(This offset is 0 for supervisor state-components, since these can only be saved with the XSAVES/XRSTORS instruction, which use compacting.)

User/supervisor state-component:
  • 0=user-state (enabled through XCR0)
  • 1=supervisor-state (enabled through IA32_XSS)
 0
1 64-byte alignment enable when state save compaction is used.

If this bit is set for a state-component, then, when storing state with compaction, padding will be inserted between the preceding state-component and this state-component as needed to provide 64-byte alignment. If this bit is not set, the state-component will be stored directly after the preceding one.

1

31:2
  		(reserved)
31:2

Attempting to query an unsupported state-component in this manner results in EAX,EBX,ECX and EDX all being set to 0.

Sub-leaves 0 and 1 of CPUID leaf 0Dh are used to provide feature information:

CPUID EAX=0Dh,ECX=0: XSAVE features
EBX ECX EDX:EAX
Maximum size (in bytes) of XSAVE save area for the set of state-components currently set in XCR0. Maximum size (in bytes) of XSAVE save area if all state-components supported by XCR0 on this CPU were enabled at the same time. 64-bit bitmap of state-components supported by XCR0 on this CPU.
CPUID EAX=0Dh,ECX=1: XSAVE extended features
EAX EBX EDX:ECX
XSAVE feature flags (see below table) Size (in bytes) of XSAVE area containing all the state-components currently set in XCR0 and IA32_XSS combined. 64-bit bitmap of state-components supported by IA32_XSS on this CPU.
EAX=0Dh,ECX=1: XSAVE feature flags in EAX
Bit EAX
Short Feature
0 xsaveopt XSAVEOPT instruction: save state-components that have been modified since last XRSTOR
1 xsavec XSAVEC instruction: save/restore state with compaction
2 xgetbv_ecx1 XGETBV with ECX=1 support
3 xss XSAVES and XRSTORS instructions and IA32_XSS MSR: save/restore state with compaction, including supervisor state.
4 xfd XFD (Extended Feature Disable) supported

31:5
  		(reserved)

Шаблон:Vpad As of July 2023, the XSAVE state-components that have been architecturally defined are:

XSAVE State-components
Index Description Enabled with
0 x87 state Шаблон:Yes
1 SSE state: XMM0-XMM15 and MXCSR rowspan=7 Шаблон:Yes
2 AVX state: top halves of YMM0 to YMM15
3 MPX state: BND0-BND3 bounds registers
4 MPX state: BNDCFGU and BNDSTATUS registers
5 AVX-512 state: opmask registers k0-k7
6 AVX-512 "ZMM_Hi256" state: top halves of ZMM0 to ZMM15
7 AVX-512 "Hi16_ZMM" state: ZMM16-ZMM31
8 Processor Trace state Шаблон:No
9 PKRU (User Protection Keys) register Шаблон:Yes
10 PASID (Process Address Space ID) state rowspan="7" Шаблон:No
11 CET_U state (Control-flow Enforcement Technology: user-mode functionality MSRs)
12 CET_S state (CET: shadow stack pointers for rings 0,1,2)
13 HDC (Hardware Duty Cycling) state
14 UINTR (User-Mode Interrupts) state
15 LBR (Last Branch Record) state
16 HWP (Hardware P-state control) state
17 AMX tile configuration state: TILECFG rowspan="3" Шаблон:Yes
18 AMX tile data registers: tmm0-tmm7
19 APX extended general-purpose registers: r16-r31[58]

20 to 61
  		(reserved)
62 Lightweight Profiling (LWP) (AMD only) Шаблон:Yes
63 (reserved)Шаблон:Efn

Шаблон:Notelist Шаблон:Vpad

EAX=12h: SGX capabilities

This leaf provides information about the supported capabilities of the Intel Software Guard Extensions (SGX) feature. The leaf provides multiple sub-leaves, selected with ECX.

Sub-leaf 0 provides information about supported SGX leaf functions in EAX and maximum supported SGX enclave sizes in EDX; ECX is reserved. EBX provides a bitmap of bits that can be set in the MISCSELECT field in the SECS (SGX Enclave Control Structure) - this field is used to control information written to the MISC region of the SSA (SGX Save State Area) when an AEX (SGX Asynchronous Enclave Exit) occurs.

CPUID EAX=12h,ECX=0: SGX leaf functions, MISCSELECT and maximum-sizes
Bit EAX EBX EDX Bit
Short Feature Short Feature Short Feature
0 sgx1 SGX1 leaf functions EXINFO MISCSELECT: report information about page fault and general protection exception that occurred inside enclave MaxEnclave­Size_Not64 Log2 of maximum enclave size supported in non-64-bit mode 0
1 sgx2 SGX2 leaf functions CPINFO MISCSELECT: report information about control protection exception that occurred inside enclave 1
2 (reserved) (reserved) 2
3 (reserved) (reserved) 3
4 (reserved) (reserved) 4
5 oss ENCLV leaves: EINCVIRTCHILD, EDECVIRTCHILD, and ESETCONTEXT (reserved) 5
6 ENCLS leaves: ETRACKC, ERDINFO, ELDBC, ELDUC (reserved) 6
7 ENCLU leaf: EVERIFYREPORT2 (reserved) 7
8 (reserved) (reserved) MaxEnclave­Size_64 Log2 of maximum enclave size supported in 64-bit mode 8
9 (reserved) (reserved) 9
10 ENCLS leaf: EUPDATESVN (reserved) 10
11 ENCLU leaf: EDECSSA (reserved) 11
12 (reserved) (reserved) 12
13 (reserved) (reserved) 13
14 (reserved) (reserved) 14
15 (reserved) (reserved) 15

31:16
  		(reserved) (reserved) (reserved)
31:16
 

Шаблон:Vpad Sub-leaf 1 provides a bitmap of which bits can be set in the 128-bit ATTRIBUTES field of SECS in EDX:ECX:EBX:EAX (this applies to the SECS copy used as input to the ENCLS[ECREATE] leaf function). The top 64 bits (given in EDX:ECX) are a bitmap of which bits can be set in the XFRM (X-feature request mask) - this mask is a bitmask of which CPU state-components (see leaf 0Dh) will be saved to the SSA in case of an AEX; this has the same layout as the XCR0 control register. The other bits are given in EAX and EBX, as follows:

CPUID EAX=12h,ECX=1: SGX settable bits in SECS.ATTRIBUTES
Bit EAX EBX Bit
Short Feature Short Feature
0 (INIT) (must be 0)Шаблон:Efn (reserved) 0
1 DEBUG Permit debugger to read and write enclave data using EDBGRD and EDBGWR 1
2 MODE64BIT 64-bit-mode enclave 2
3 (reserved) 3
4 PROVISIONKEY Provisioning key available from EGETKEY 4
5 EINITTOKEN_KEY EINIT token key available from EGETKEY 5
6 CET CET (Control-Flow Enforcement Technology) attributes enable 6
7 KSS Key Separation and Sharing 7
8 (reserved) 8
9 (reserved) 9
10 AEXNOTIFY Threads inside enclave may receive AEX notifications 10

31:11
  		(reserved)
31:11
 

Шаблон:Notelist Шаблон:Vpad Sub-leaves 2 and up are used to provide information about which physical memory regions are available for use as EPC (Enclave Page Cache) sections under SGX.

CPUID EAX=12h,ECX≥2: SGX Enclave Page Cache section information
Bits EAX EBX ECX EDX Bits
3:0 Sub-leaf type:
  • 0000: Invalid
  • 0001: EPC section
  • other: reserved
 Bits 51:32 of physical base address of EPC section EPC Section properties:
  • 0000: Invalid
  • 0001: Has confidentiality and integrity protection
  • 0010: Has confidentiality protection only
  • other: reserved
 Bits 51:32 of size of EPC section 3:0

11:4
  		(reserved) (reserved)
11:4
 

19:12
  		Bits 31:12 of physical base address of EPC section Bits 31:12 of size of EPC section
19:12
 

31:20
  		(reserved) (reserved)
31:20
 

Шаблон:Vpad

EAX=14h, ECX=0: Processor Trace

This sub-leaf provides feature information for Intel Processor Trace (also known as Real Time Instruction Trace).

The value returned in EAX is the index of the highest sub-leaf supported for CPUID with EAX=14h. EBX and ECX provide feature flags, EDX is reserved.

CPUID EAX=14h,ECX=0: Processor Trace feature bits in EBX and ECX
Bit EBX ECX Bit
Short Feature Short Feature
0 CR3 filtering supported topaout ToPA (Table of Physical Addresses) output mechanism for trace packets supported 0
1 Configurable PSB (Packet Stream Boundary) packet rate and Cycle-Accurate Mode (CYC packets) supported mentry ToPA tables can contain hold multiple output entries 1
2 IP filtering, TraceStop filtering and preservation of PT MSRs across warm reset supported snglrngout Single-Range Output scheme supported 2
3 MTC (Mini Time Counter) timing packets supported, and suppression of COFI (Change of Flow Instructions) packets supported. Output to Trace Transport subsystem supported 3
4 ptwrite PTWRITE instruction supported (reserved) 4
5 Power Event Trace supported (reserved) 5
6 Preservation of PSB and PMI (performance monitoring interrupt) supported (reserved) 6
7 Event Trace packet generation supported (reserved) 7
8 TNT (Branch Taken-Not-Taken) packet generation disable supported. (reserved) 8

30:9
  		(reserved) (reserved)
30:9
 
31 (reserved) IP (Instruction Pointer) format for trace packets that contain IP payloads:
  • 0=RIP (effective-address IP)
  • 1=LIP (linear-address IP, with CS base address added)
 31

EAX=19h: AES Key Locker features

This leaf provides feature information for AES Key Locker in EAX, EBX and ECX. EDX is reserved.

CPUID EAX=19h: Key Locker feature bits in EAX, EBX and ECX
Bit EAX EBX ECX Bit
Short Feature Short Feature Short Feature
0 Key Locker restriction of CPL0-only supported aes_kle AES "Key Locker" Instructions No-backup parameter to LOADIWKEY supported 0
1 Key Locker restriction of no-encrypt supported (reserved) KeySource encoding of 1 (randomization of internal wrapping key) supported 1
2 Key Locker restriction of no-decrypt supported aes_wide_kl AES "Wide Key Locker" Instructions (reserved) 2
3 (reserved) (reserved) (reserved) 3
4 (reserved) kl_msrs "Key Locker" MSRs (reserved) 4

31:5
  		(reserved) (reserved) (reserved)
31:5
 

Шаблон:Vpad

EAX=24h, ECX=0: AVX10 Features

This returns a maximum supported sub-leaf in EAX and AVX10 feature information in EBX.[57] (ECX and EDX are reserved.)

CPUID EAX=24h, ECX=0: AVX10 feature bits in EBX
Bit EBX
Short Feature
7:0 AVX10 Converged Vector ISA version (≥1)
15:8 (reserved)
16 avx10-128 128-bit vector support is present
17 avx10-256 256-bit vector support is present
18 avx10-512 512-bit vector support is present
31:19 (reserved)

EAX=80000000h: Get Highest Extended Function Implemented

The highest calling parameter is returned in EAX.

EBX/ECX/EDX return the manufacturer ID string (same as EAX=0) on AMD but not Intel CPUs.

EAX=80000001h: Extended Processor Info and Feature Bits

This returns extended feature flags in EDX and ECX.

Many of the bits in EDX (bits 0 through 9, 12 through 17, 23, and 24) are duplicates of EDX from the EAX=1 leaf - these bits are highlighted in light yellow. (These duplicated bits are present on AMD but not Intel CPUs.)

AMD feature flags are as follows:[61][62]

CPUID EAX=80000001h: Feature bits in EDX and ECX
Bit EDX ECX Bit
Short Feature Short Feature
0 fpu Шаблон:Some lahf_lm LAHF/SAHF in long mode 0
1 vme Шаблон:Some cmp_legacy Hyperthreading not valid 1
2 de Шаблон:Some svm Secure Virtual Machine 2
3 pse Шаблон:Some extapic Extended APIC space 3
4 tsc Шаблон:Some cr8_legacy CR8 in 32-bit mode 4
5 msr Шаблон:Some abm/lzcnt Advanced bit manipulation (LZCNT and POPCNT) 5
6 pae Шаблон:Some sse4a SSE4a 6
7 mce Шаблон:Some misalignsse Misaligned SSE mode 7
8 cx8 Шаблон:Some 3dnowprefetch PREFETCH and PREFETCHW instructions 8
9 apic Шаблон:Some osvw OS Visible Workaround 9
10 (syscall)Шаблон:Efn (SYSCALL/SYSRET, K6 only) ibs Instruction Based Sampling 10
11 syscallШаблон:Efn SYSCALL and SYSRET instructions xop XOP instruction set 11
12 mtrr Шаблон:Some skinit SKINIT/STGI instructions 12
13 pge Шаблон:Some wdt Watchdog timer 13
14 mca Шаблон:Some (reserved) 14
15 cmov Шаблон:Some lwp Light Weight Profiling[63] 15
16 patШаблон:Efn Шаблон:Some fma4 4-operand fused multiply-add instructions 16
17 pse36 Шаблон:Some tce Translation Cache Extension 17
18 (reserved) (reserved) 18
19 ecc "Athlon MP" / "Sempron" CPU brand identificationШаблон:Efn nodeid_msr NodeID MSR (C001_100C)[64] 19
20 nx NX bit (reserved) 20
21 (reserved) tbm Trailing Bit Manipulation 21
22 mmxext Extended MMX topoext Topology Extensions 22
23 mmx Шаблон:Some perfctr_core Core performance counter extensions 23
24 fxsrШаблон:Efn Шаблон:Some perfctr_nb Northbridge performance counter extensions 24
25 fxsr_opt FXSAVE/FXRSTOR optimizations (StreamPerfMon) (Streaming performance monitor architecture)Шаблон:Efn 25
26 pdpe1gb Gigabyte pages dbx Data breakpoint extensions 26
27 rdtscp RDTSCP instruction perftsc Performance timestamp counter (PTSC) 27
28 (reserved) pcx_l2i L2I perf counter extensions 28
29 lm Long mode monitorx MONITORX and MWAITX instructions 29
30 3dnowext Extended 3DNow! addr_mask_ext Address mask extension to 32 bits for instruction breakpoints 30
31 3dnow 3DNow! (reserved) 31

Шаблон:Notelist Шаблон:Vpad

EAX=80000002h,80000003h,80000004h: Processor Brand String

These return the processor brand string in EAX, EBX, ECX and EDX. CPUID must be issued with each parameter in sequence to get the entire 48-byte ASCII processor brand string.[65] It is necessary to check whether the feature is present in the CPU by issuing CPUID with EAX = 80000000h first and checking if the returned value is not less than 80000004h.

The string is specified in Intel/AMD documentation to be null-terminated, however this is not always the case (e.g. DM&P Vortex86DX3 and AMD Ryzen 7 6800HS are known to return non-null-terminated brand strings in leaves 80000002h-80000004h[66][67]), and software should not rely on it. 

#include <stdio.h>
#include <string.h>
#include <cpuid.h>

int main()
{
    unsigned int regs[12];
    char str[sizeof(regs)+1];

    __cpuid(0x80000000, regs[0], regs[1], regs[2], regs[3]);

    if (regs[0] < 0x80000004)
        return 1;

    __cpuid(0x80000002, regs[0], regs[1], regs[2], regs[3]);
    __cpuid(0x80000003, regs[4], regs[5], regs[6], regs[7]);
    __cpuid(0x80000004, regs[8], regs[9], regs[10], regs[11]);

    memcpy(str, regs, sizeof(regs));
    str[sizeof(regs)] = '\0';
    printf("%s\n", str);

    return 0;
}

EAX=80000005h: L1 Cache and TLB Identifiers

This function contains the processor's L1 cache and TLB characteristics.

EAX=80000006h: Extended L2 Cache Features

Returns details of the L2 cache in ECX, including the line size in bytes (Bits 07 - 00), type of associativity (encoded by a 4 bits field; Bits 15 - 12) and the cache size in KB (Bits 31 - 16). 

#include <stdio.h>
#include <cpuid.h>

int main()
{
    unsigned int eax, ebx, ecx, edx;
    unsigned int lsize, assoc, cache;

    __cpuid(0x80000006, eax, ebx, ecx, edx);
    
    lsize = ecx & 0xff;
    assoc = (ecx >> 12) & 0x07;
    cache = (ecx >> 16) & 0xffff;

    printf("Line size: %d B, Assoc. type: %d, Cache size: %d KB.\n", lsize, assoc, cache);

    return 0;
}

EAX=80000007h: Processor Power Management Information and RAS Capabilities

This function provides information about power management, power reporting and RAS (Reliability, availability and serviceability) capabilities of the CPU.

CPUID EAX=80000007h: RAS features in EBX and power management features in EDX
Bit EBX EDX Bit
Short Feature Short Feature
0 MCAOverflowRecov MCA (Machine Check Architecture) overflow recovery support TS Temperature Sensor 0
1 SUCCOR Software uncorrectable error containment and recovery capability FID Frequency ID Control 1
2 HWA Hardware assert support (MSRs C001_10C0 to C001_10DF VID Voltage ID Control 2
3 ScalableMca Scalable MCA supported TTP THERMTRIP 3
4 (reserved) TM Hardware thermal control (HTC) supported 4
5 (reserved) STC Software thermal control (STC) supported[68] 5
6 (reserved) 100MHzSteps 100 MHz multiplier control 6
7 (reserved) HwPstate Hardware P-state control (MSRs C001_0061 to C001_0063) 7
8 (reserved) TscInvariant Invariant TSC - TSC (Time Stamp Counter) rate is guaranteed to be invariant across all P-states, C-states and sop grant transitions. 8
9 (reserved) CPB Core Performance Boost 9
10 (reserved) EffFreqRO Read-only effective frequency interface (MSRs C000_00E7 and C000_00E8) 10
11 (reserved) ProcFeedback­Interface Processor Feedback Interface supported 11
12 (reserved) ProcPower­Reporting Processor power reporting interface supported 12
13 (reserved) Connected­Standby Connected Standby[69] 13
14 (reserved) RAPL Running Average Power Limit 14
15 (reserved) FastCPPC Fast CPPC (Collaborative Processor Performance Control) supported 15

31:16
  		(reserved) (reserved)
31:16
 
CPUID EAX=80000007h: Processor Feedback info in EAX and power monitoring interface info in ECX
Bits EAX ECX Bits
Short Feature Short Feature
7:0 NumberOfMonitors Number of Processor Feedback MSR pairs available, starting from MSR C001_0080 onwards[70] CpuPwrSample­TimeRatio Ratio of compute unit power accumulator sample period to TSC counter period. 7:0
15:8 Version Processor Feedback Capabilities version 15:8
31:16 MaxWrapTime Maximum time between reads (in milliseconds) that software should use to avoid two wraps. 31:16

EAX=80000008h: Virtual and Physical address Sizes

CPUID EAX=80000008h: Feature bits in EBX
Bit EBX
Short Feature
0 clzero CLZERO instruction
1 retired_instr Retired instruction count MSR (C000_00E9h) supported
2 xrstor_fp_err XRSTOR restores FP errors
3 invlpgb INVLPGB and TLBSYNC instructions
4 rdpru RDPRU instruction
5 (reserved)
6 mbe Memory Bandwidth Enforcement
7 (reserved)
8 mcommit MCOMMIT instruction
9 wbnoinvd WBNOINVD instruction
10 (reserved)
11 (reserved)
12 IBPB Indirect Branch Prediction Barrier (performed by writing 1 to bit 0 of PRED_CMD (MSR 049h))
13 wbinvd_int WBINVD and WBNOINVD are interruptible
14 IBRS Indirect Branch Restricted Speculation
15 STIBP Single Thread Indirect Branch Prediction mode
16 IbrsAlwaysOn IBRS mode has enhanced performance and should be left always on
17 StibpAlwaysOn STIBP mode has enhanced performance and should be left always on
18 ibrs_preferred IBRS preferred over software
19 ibrs_same_mode_protection IBRS provides Same Mode Protection
20 no_efer_lmsle EFER.LMSLE is unsupportedШаблон:Efn
21 invlpgb_nested INVLPGB support for nested pages
22 (reserved)
23 ppin Protected Processor Inventory Number -

PPIN_CTL (C001_02F0) and PPIN (C001_02F1) MSRs are present

24 ssbd Speculative Store Bypass Disable
25 ssbd_legacy Speculative Store Bypass Disable Legacy
26 ssbd_no Speculative Store Bypass Disable Not Required
27 cppc Collaborative Processor Performance Control
28 psfd Predictive Store Forward Disable
29 btc_no Branch Type Confusion: Processor not affected
30 IBPB_RET IBPB (see bit 12) also clears return address predictor
31 branch_sampling Branch Sampling Support[71]
CPUID EAX=80000008h: Size and range fields in EAX, ECX, EDX
Bits EAX ECX EDX Bits
7:0 Number of Physical Address Bits Number of Physical Cores (minus 1) Maximum page count for INVLPGB instruction 7:0
11:8 Number of Linear Address Bits (reserved) 11:8
15:12 APIC ID Size 15:12
17:16 Guest Physical Address SizeШаблон:Efn Performance Timestamp Counter size Maximum ECX value recognized by RDPRU instruction 17:16
23:18 (reserved) 23:18
31:24 (reserved) 31:24

Шаблон:Notelist Шаблон:Vpad

EAX=8000000Ah: Secure Virtual Machine features

This leaf returns information about AMD SVM (Secure Virtual Machine) features in EAX, EBX and EDX.

CPUID EAX=8000000Ah: SVM information in EAX, EBX and ECX
Bits EAX EBX ECX Bits
7:0 SVM Revision Number Number of available ASIDs
(address space identifiers) 		(reserved) 7:0
8 (hypervisor)Шаблон:Efn 8
31:9 (reserved) 31:9

Шаблон:Vpad

CPUID EAX=8000000Ah: SVM feature flags in EDX
Bit EDX
Short Feature
0 NP Rapid Virtualization Indexing (Nested Paging)
1 LbrVirt LBR (Last Branch Records) virtualization
2 SVML SVM-Lock
3 NRIPS nRIP (next sequential instruction pointer) save on #VMEXIT supported
4 TscRateMsr MSR-based TSC rate control (MSR C000_0104h)
5 VmcbClean VMCB (Virtual Machine Control Block) clean bits supported
6 FlushByAsid TLB flush events (e.g. CR3 writes, CR4.PGE toggles) only flush the TLB entries of the current ASID (address space ID)
7 DecodeAssist Decode assists supported
8 (reserved)
9 (SseIsa10Compat)Шаблон:Efn (reserved)
10 PauseFilter PAUSE intercept filter supported
11 (reserved)
12 PauseFilter­Threshold PAUSE filter cycle count threshold supported
13 AVIC AMD Advanced Virtualized Interrupt Controller supported
14 (reserved)
15 VMSAVEvirt VMSAVE and VMLOAD virtualization
16 VGIF Global Interrupt Flag (GIF) virtualization
17 GMET Guest Mode Execution Trap
18 x2AVIC x2APIC mode supported for AVIC
19 SSSCheck SVM Supervisor shadow stack restrictions
20 SpecCtrl SPEC_CTRL (MSR 2E0h) virtualization
21 ROGPT Read-Only Guest Page Table supported
22 (reserved)
23 HOST_MCE_­OVERRIDE Guest mode Machine-check exceptions when host CR4.MCE=1 and guest CR4.MCE=0 cause intercepts instead of shutdowns
24 TlbiCtl INVLPGB/TLBSYNC hypervisor enable in VMCB and TLBSYNC intercept support
25 VNMI NMI (Non-Maskable interrupt) virtualization
26 IbsVirt IBS (Instruction-Based Sampling) virtualization
27 ExtLvtOffset­FaultChg Read/Write fault behavior for extended LVT offsets (APIC addresses 0x500-0x530) changed to Read Allowed, Write #VMEXIT[72]
28 VmcbAddr­ChkChg VMCB address check change[72]
29 BusLock­Threshold Bus Lock Threshold
30 (reserved)
31 (reserved)

Шаблон:Notelist

Шаблон:Vpad

EAX=8000001Fh: Encrypted Memory Capabilities

CPUID EAX=8000001Fh: Encrypted Memory feature bits in EAX
Bit EAX
Short Feature
0 SME Secure Memory Encryption
1 SEV Secure Encrypted Virtualization
2 PageFlushMSR Page flush MSR (C001_011Eh) supported
3 SEV-ES SEV Encrypted State
4 SEV-SNP SEV Secure Nested Paging
5 VMPL VM Privilege Levels
6 RMPQUERY RMPQUERY instruction supported
7 VmplSSS VMPL Supervisor shadow stack supported
8 SecureTSC Secure TSC supported
9 TscAux­Virtualization Virtualization of TSC_AUX MSR (C000_0103) supported
10 HwEnfCacheCoh Hardware cache coherency across encryption domains enforced
11 64BitHost SEV Guest execution only allowed from 64-bit host
12 Restricted­Injection SEV-ES guests can refuse all event-injections except #HV (Hypervisor Injection Exception)
13 Alternate­Injection SEV-ES guests can use an encrypted VMCB field for event-injection
14 DebugSwap Full debug state swap supported for SEV-ES guests
15 PreventHostIBS Prevent host IBS for a SEV-ES guest
16 VTE Virtual Transparent Encryption for SEV
17 Vmgexit­Parameter VMGEXIT parameter is supported (using the RAX register)
18 VirtualTomMsr Virtual TOM (top-of-memory) MSR (C001_0135) supported
19 IbsVirtGuestCtl IBS state virtualization is supported for SEV-ES guests
20 (reserved)
21 (reserved)
22 (reserved)
23 (reserved)
24 VmsaRegProt VMSA (VM Save Area) register protection supported
25 SmtProtection SMT Protection supported
26 (reserved)
27 (reserved)
28 SVSMComm­PageMSR SVSM (Secure VM Service Module[73]) communication page MSR (C001_F000h) supported
29 NestedVirt­SnpMsr VIRT_RMPUPDATE (C001_F001h) and VIRT_PSMASH (C001_F002h) MSRs supported
30 (reserved)
31 (reserved)
CPUID EAX=8000001Fh: Encrypted Memory feature information in EBX, ECX and EDX
Bits EBX ECX EDX Bits
5:0 C-bit (encryption enable bit) location in page table entry Maximum ASID value that can be used for a SEV-enabled guest (maximum number of encrypted guests that can be supported simultaneously) Minimum ASID value for a guest that is SEV-enabled but not SEV-ES-enabled 5:0
11:6 Physical address width reduction when memory encryption is enabled 11:6
15:12 Number of VMPLs (VM Privilege Levels) supported 15:12
31:16 (reserved) 31:16

Шаблон:Vpad

EAX=80000021h: Extended Feature Identification 2

CPUID EAX=80000021h: Extended feature bits in EAX
Bit EAX
Short Feature
0 NoNestedDataBp Processor ignores nested data breakpoints
1 FsGsKernelGsBase­NonSerializing WRMSR to the FS_BASE, GS_BASE and KernelGSBase MSRs is non-serializing[74]
2 LFenceAlways­Serializing LFENCE is always dispatch serializing
3 SmmPgCfgLock SMM paging configuration lock supported
4 (reserved)
5 (reserved)
6 NullSelect­ClearsBase Null segment selector loads also clear the destination segment register base and limit
7 UpperAddress­Ignore Upper Address Ignore is supported
8 AutomaticIBRS Automatic IBRS
9 NoSmmCtlMSR SMM_CTL MSR (C0010116h) is not supported
10 FSRS Fast short Шаблон:Nowrap supported
11 FSRC Fast short Шаблон:Nowrap supported
12 (reserved)
13 PrefetchCtlMsr PrefetchControl MSR (C0000108h) is supported
14 (reserved)
15 (reserved)
16 (reserved)
17 CpuidUserDis CPUID disable for non-privileged software
18 EPSF Enhanced Predictive Store Forwarding supported
31:19 (reserved)
CPUID EAX=80000021h: Extended feature information in EBX
Bit EBX
Short Feature
11:0 MicrocodePatchSize The size of the Microcode patch in 16-byte multiples. If 0, the size of the patch is at most 5568 (15C0h) bytes
31:12 (reserved)

EAX=8FFFFFFFh: AMD Easter Egg

Several AMD CPU models will, for CPUID with EAX=8FFFFFFFh, return an Easter Egg string in EAX, EBX, ECX and EDX.[75][76] Known Easter Egg strings include:

Processor String
AMD K6 NexGen‍erationAMD
AMD K8 IT'S HAMMER TIME
AMD Jaguar[77] HELLO KITTY! ^-^

EAX=C0000000h: Get Highest Centaur Extended Function

Returns index of highest Centaur leaf in EAX. If the returned value in EAX is less than C0000001h, then Centaur extended leaves are not supported.

Present in CPUs from VIA and Zhaoxin.

On IDT WinChip CPUs (CentaurHauls Family 5), the extended leaves C0000001h-C0000005h do not encode any Centaur-specific functionality but are instead aliases of leaves 80000001h-80000005h.[78]

EAX=C0000001h: Centaur Feature Information

This leaf returns Centaur feature information (mainly VIA PadLock) in EDX.[79][80] (EAX, EBX and ECX are reserved.)

CPUID EAX=C0000001h: Centaur feature bits in EDX
Bit EDX
Short Feature
0 sm2Шаблон:Efn SM2 present
1 sm2_enШаблон:Efn SM2 enabled
2 rng PadLock RNG present: XSTORE and Шаблон:Nowrap instructions
3 rng_en RNG enabled
4 ccsШаблон:Efn PadLock SM3/SM4 instructions present: CCS_HASH and CCS_ENCRYPT
5 ccs_enШаблон:Efn SM3/SM4 instructions enabled
6 xcrypt PadLock Advanced Cryptographic Engine (ACE, using AES cipher) present: Шаблон:Nowrap instructions
7 xcrypt_en ACE enabled
8 ace2 ACE v2 present: Шаблон:Nowrap instruction, as well as support for digest mode and misaligned data for ACE's Шаблон:Nowrap instructions.
9 ace2_en ACE v2 enabled
10 phe PadLock Hash Engine (PHE): Шаблон:Nowrap and Шаблон:Nowrap instructions
11 phe_en PHE enabled
12 pmm PadLock Montgomery Multiplier (PMM): Шаблон:Nowrap instruction
13 pmm_en PMM enabled
14 (reserved)
15 zx_fma FMA supported
16 parallax Adaptive P-state control present
17 parallax_en Adaptive P-state control enabled
18 overstress Overstress feature for auto overclock present
19 overstress_en Overstress feature for auto overclock enabled
20 tm3 Thermal Monitor 3 present
21 tm3_en Thermal Monitor 3 enabled
22 rng2 RNG v2: Second generation RNG present
23 rng2_en RNG v2 enabled
24 sem SME feature present
25 phe2 PHE v2: SHA384 and SHA512 present
26 phe2_en PHE v2 enabled
27 xmodx RSA instructions present: XMODEXP and MONTMUL2
28 xmodx_en RSA instructions enabled
29 vex VEX instructions present
30 vex_en VEX instructions enabled
31 stk STK is present

Шаблон:Notelist

CPUID usage from high-level languages

Inline assembly

This information is easy to access from other languages as well. For instance, the C code for gcc below prints the first five values, returned by the cpuid: 

#include <stdio.h>
#include <cpuid.h>

int main()
{
    unsigned int i, eax, ebx, ecx, edx;

    for (i = 0; i < 5; i++) {
        __cpuid(i, eax, ebx, ecx, edx);
        printf ("InfoType %x\nEAX: %x\nEBX: %x\nECX: %x\nEDX: %x\n", i, eax, ebx, ecx, edx);
    }

    return 0;
}

In MSVC and Borland/Embarcadero C compilers (bcc32) flavored inline assembly, the clobbering information is implicit in the instructions: 

#include <stdio.h>

int main()
{
    unsigned int a, b, c, d, i = 0;

    __asm {
        /* Do the call. */
        mov EAX, i;
        cpuid;
        /* Save results. */
        mov a, EAX;
        mov b, EBX;
        mov c, ECX;
        mov d, EDX;
    }

    printf ("InfoType %x\nEAX: %x\nEBX: %x\nECX: %x\nEDX: %x\n", i, a, b, c, d);
    return 0;
}

If either version was written in plain assembly language, the programmer must manually save the results of EAX, EBX, ECX, and EDX elsewhere if they want to keep using the values.

Wrapper functions

GCC also provides a header called <cpuid.h> on systems that have CPUID. The __cpuid is a macro expanding to inline assembly. Typical usage would be: 

#include <stdio.h>
#include <cpuid.h>

int main()
{
    unsigned int eax, ebx, ecx, edx;

    __cpuid(0 /* vendor string */, eax, ebx, ecx, edx);
    printf("EAX: %x\nEBX: %x\nECX: %x\nEDX: %x\n", eax, ebx, ecx, edx);

    return 0;
}

But if one requested an extended feature not present on this CPU, they would not notice and might get random, unexpected results. Safer version is also provided in <cpuid.h>. It checks for extended features and does some more safety checks. The output values are not passed using reference-like macro parameters, but more conventional pointers. 

#include <stdio.h>
#include <cpuid.h>

int main()
{
    unsigned int eax, ebx, ecx, edx;

    /* 0x81234567 is nonexistent, but assume it exists */
    if (!__get_cpuid (0x81234567, &eax, &ebx, &ecx, &edx)) {
        printf("Warning: CPUID request 0x81234567 not valid!\n");
        return 1;
    }

    printf("EAX: %x\nEBX: %x\nECX: %x\nEDX: %x\n", eax, ebx, ecx, edx);

    return 0;
}

Notice the ampersands in &a, &b, &c, &d and the conditional statement. If the __get_cpuid call receives a correct request, it will return a non-zero value, if it fails, zero.[81]

Microsoft Visual C compiler has builtin function __cpuid() so the cpuid instruction may be embedded without using inline assembly, which is handy since the x86-64 version of MSVC does not allow inline assembly at all. The same program for MSVC would be: 

#include <stdio.h>
#ifdef __MSVC__
    #include <intrin.h>
#endif

int main()
{
    unsigned int regs[4];
    int i;

    for (i = 0; i < 4; i++) {
        __cpuid(regs, i);
        printf("The code %d gives %d, %d, %d, %d", regs[0], regs[1], regs[2], regs[3]);
    }

    return 0;
}

Many interpreted or compiled scripting languages are capable of using CPUID via an FFI library. One such implementation shows usage of the Ruby FFI module to execute assembly language that includes the CPUID opcode.

.NET 5 and later versions provide the System.Runtime.Intrinsics.X86.X86base.CpuId method. For instance, the C# code below prints the processor brand if it supports CPUID instruction:

using System.Runtime.InteropServices;
using System.Runtime.Intrinsics.X86;
using System.Text;

namespace X86CPUID {
    class CPUBrandString {
        public static void Main(string[] args) {
            if (!X86Base.IsSupported) {
                Console.WriteLine("Your CPU does not support CPUID instruction.");
            } else {
                Span<int> raw = stackalloc int[12];
                (raw[0], raw[1], raw[2],  raw[3])  = X86Base.CpuId(unchecked((int)0x80000002), 0);
                (raw[4], raw[5], raw[6],  raw[7])  = X86Base.CpuId(unchecked((int)0x80000003), 0);
                (raw[8], raw[9], raw[10], raw[11]) = X86Base.CpuId(unchecked((int)0x80000004), 0);

                Span<byte> bytes = MemoryMarshal.AsBytes(raw);
                string brand = Encoding.UTF8.GetString(bytes).Trim();
                Console.WriteLine(brand);
            }
        }
    }
}

CPU-specific information outside x86

Some of the non-x86 CPU architectures also provide certain forms of structured information about the processor's abilities, commonly as a set of special registers:

  • ARM architectures have a CPUID coprocessor register which requires exception level EL1 or above to access.[82]
  • The IBM System z mainframe processors have a Store CPU ID (STIDP) instruction since the 1983 IBM 4381[83] for querying the processor ID.[84]
  • The IBM System z mainframe processors also have a Store Facilities List Extended (STFLE) instruction which lists the installed hardware features.[84]
  • The MIPS32/64 architecture defines a mandatory Processor Identification (PrId) and a series of daisy-chained Configuration Registers.[85]
  • The PowerPC processor has the 32-bit read-only Processor Version Register (PVR) identifying the processor model in use. The instruction requires supervisor access level.[86]

DSP and transputer-like chip families have not taken up the instruction in any noticeable way, in spite of having (in relative terms) as many variations in design. Alternate ways of silicon identification might be present; for example, DSPs from Texas Instruments contain a memory-based register set for each functional unit that starts with identifiers determining the unit type and model, its ASIC design revision and features selected at the design phase, and continues with unit-specific control and data registers. Access to these areas is performed by simply using the existing load and store instructions; thus, for such devices, there is no need for extending the register set for device identification purposes.Шаблон:Citation needed

See also

References

Шаблон:Reflist

Further reading

External links

Шаблон:Multimedia extensions

Партнерские ресурсы
Криптовалюты
Магазины
Хостинг
Разное

  1. ↑ Шаблон:Cite web
  2. ↑ Шаблон:Cite web
  3. ↑ Шаблон:Cite web
  4. ↑ Шаблон:Cite web
  5. ↑ Шаблон:Cite tweet
  6. ↑ instlatx64, CPUID dump for RDC IAD 100. Retrieved 22 December 2022.
  7. ↑ 7,0 7,1 7,2 7,3 smxi, Inxi issue 197: Elbrus CPU support data and implementation. Retrieved 23 October 2023. Archived on 23 October 2023.
  8. ↑ Шаблон:Cite web
  9. ↑ 9,0 9,1 Шаблон:Cite web
  10. ↑ Шаблон:Cite web
  11. ↑ Шаблон:Cite web
  12. ↑ Шаблон:Cite web
  13. ↑ Шаблон:Cite web
  14. ↑ iXBT Labs, VIA Nano CPUID Tricks, Aug 26, 2010. Archived on Aug 29, 2010.
  15. ↑ IDT, WinChip 2A data sheet, v1.0, Jan 1999, page A-3.
  16. ↑ VIA, C3 Nehemiah Datasheet, rev 1.13, Sep 29, 2004, page A-3.
  17. ↑ Agner Fog, CpuIDFake, v1.00, Jan 22, 2010, see "Instructions.txt". Archived on Jul 9, 2010.
  18. ↑ Transmeta, Crusoe BIOS Programmer's Guide, Jan 23, 2004, page 65.
  19. ↑ AMD, Geode LX Data Book, pub.id. 33234H, Feb. 2009, page 107. Archived on Dec 3, 2023.
  20. ↑ DM&P, Vortex86EX2_A9133_Master_Data_Sheet_V11_BF, May 8, 2019, page 72.
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  22. ↑ Intel, Pentium Processor Family Developer's Manual, 1997, order no. 241428-005, sections 3.4.1.2 (page 91), 17.5.1 (page 489) and appendix A (page 522) provide more detail on how the "processor type" field and the "dual processor" designation work.
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